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STMPE821
8-bit Xpander LogicTM with touchkey controller
Preliminary Data
Features

Up to 8 GPIOs Up to 8 touchkey capacitive touch inputs Operating voltage 1.8 - 5.5 V Internal regulator Interrupt output pin I2C interface 8 kV HBM ESD protection 40 fF resolution, 128 steps capacitance measurement (5.0 pF dynamic range) Advanced data filtering (AFS) Environment tracking calibration (ETC) Individually adjustable touch variance (TVR) setting for all channels Adjustable environmental variance (EVR) for optimal calibration
QFN16L (2.6 x 1.8 mm)
Applications

Description
The STMPE821 is a GPIO (general purpose input/output) port expander able to interface a main digital ASIC via the two-line bidirectional bus (I2C). A separate GPIO expander is often used in mobile multimedia platforms to solve the problems of the limited amount of GPIOs typically available on the digital engine. The STMPE821 offers great flexibility, as each I/O can be configured as input, output or specific functions. The device has been designed with very low quiescent current and includes a wakeup feature for each I/O, to optimize the power consumption of the device.
Mobile and smart phones Portable media players Game consoles
Table 1.
Device summary
Order code STMPE821QTR Package QFN16L (2.6 x 1.8 mm) Packing Tape and reel
June 2008
Rev 2
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STMPE821
Contents
1 STMPE821 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 1.3 STMPE821 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin assignment and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 STMPE821 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Capacitive compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 2.1.2 Noise filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4 5 6 7 8 9 10
Power schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register map and function description . . . . . . . . . . . . . . . . . . . . . . . . . 13 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt controller module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Capacitive touch module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.1 10.2 PWM function register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt on basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11 12 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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STMPE821
Contents
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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STMPE821 functional overview
STMPE821
1
STMPE821 functional overview
The STMPE821 consists of the following blocks:

GPIO controller PWM controller Impedance sensor Touchkey controller I2C interface
1.1
STMPE821 block diagram
Figure 1. Functional block diagram
GPIO controller
GPIO 0 - 7 /Touch 0 - 7
PWM controller
Impedance sensor
INT RST SCLK SDAT 2 IC interface Touchkey controller ARef
GND
VCC
VIO
CS00046
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STMPE821
STMPE821 functional overview
1.2
Pin assignment and function
Figure 2. STMPE821 pin assignment (top view)
12 13 14
11
10
9 8 7
STMPE821 15 16 1 2 3 4 6 5
CS00045
Table 2.
Pin assignments and function
Pin name GPIO_2/Touch_2 GPIO_1/Touch_1 GPIO_0/Touch_0 ARef RST SDA SCL INT GND VCC VIO GPIO_7/Touch_7 GPIO_6/Touch_6 GPIO_5/Touch_5 GPIO_4/Touch_4 GPIO_3/Touch_3 GPIO 2 GPIO 1 GPIO 0 Reference capacitor for touch sensor RESET (active low) I2C data I2C clock INT output GND Supply voltage for I2C block Supply voltage for GPIO and internal regulator GPIO 7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 Description
Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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STMPE821 functional overview
STMPE821
1.3
STMPE821 typical application
The STMPE821 is able to support up to 8 channel capacitive sensors. Figure 3. Typical application diagram
STMPE821
RST INT Baseband/CPU SCLK SDAT ARef
CS00047
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STMPE821
Capacitive compensation
2
Capacitive compensation
The STMPE821 is capable to measuring up to 5.0 pF in capacitance difference between the reference point (Zref) and the individual channels. In the case where the PCB connection between the sensor pads and the device is too long, the "REFERENCE DELAY" register is able to shift the reference by up to 5.0 pF, allowing the TOUCH channels to measure added capacitance 5.0 pF with offset of 5.0 pF, as shown in following diagram. In case this is still not enough to compensate for the capacitance on sensor lines (due to very long sensor trace), an external capacitor of up to 30 pF can be connected at the A_Ref pin. This allows to further shift up the dynamic range of the capacitance measurement. Figure 4.
5.0 pF
Capacitance compensation
Reference delay register = 0 Dynamic range = 0 - 5.0 pF
5.0 pF
5.0 pF
Reference delay register = 5.0 pF Dynamic range = 5.0 - 10.0 pF
5.0 pF
30.0pF
5.0 pF
Reference delay = 5.0 pF ARef = 30 pF Dynamic range = 35.0 - 40.0 pF
Increasing capacitance
CS00052
The sensed capacitance is accessible to host through the "IMPEDANCE" registers.
2.1
Calibration algorithm
The STMPE821 maintains 2 parameters for each TOUCH channel: TVR and CALIBRATED IMPEDANCE. CALIBRATED IMPEDANCE is an internal reference of which, if the currently measured IMPEDANCE exceeds the CALIBRATED IMPEDANCE by a magnitude of TVR, it is considered a TOUCH. If the IMPEDANCE is more than the CALIBRATED IMPEDANCE, but the magnitude does not exceed CALIBRATED IMPEDANCE by TVR, it is not considered a TOUCH. In this case, 2 scenarios are possible: 1. Environmental changes has caused the IMPEDANCE to increase 2. Finger is near the sensing pad, but not near enough In case 1, the change in IMPEDANCE is expected to be small, as environmental changes are normally gradual. A value "EVR" is maintained to specify the maximum IMPEDANCE change that is still considered an environmental change.
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Capacitive compensation Table 3. Calibration action under different scenarios
Scenario IMP>CALIBRATED IMP + TVR No touch, no calibration IMPCALIBRATED IMP + EVR IMPCALIBRATED IMP IMPSTMPE821
Touch sensing and calibration action Touch sensing and calibration action
ETC WAIT register state a period of time of which, all TOUCH inputs must remain "NO TOUCH" for the next calibration to be carried out. CAL INTERVAL states the period of time between successive calibrations when there are prolonged NO TOUCH condition.
2.1.1
Noise filtering
When the STMPE821 is operating in the vicinity of highly emissive circuits (DC-DC converter, PWM controller/drive etc), the sensor inputs will be affected by high-frequency noise. In this situation, the time-integrating function could be used to distinguish between real touch, or emission-related false touch. The INTEGRATION TIME and STRENGTH THRES registers are used to configure the timeintegrating function of STMPE821.
2.1.2
Data filtering
The output from the calibration unit is an instantaneous "TOUCH" or "NO TOUCH" status. This output is directed to the filtering stage where the TOUCH is integrated across a programmable period of time. The output of the integration stage would be a "STRENGTH" (in STRENGTH register) that indicates the number of times a "TOUCH" is seen, across the integration period. The "STRENGTH" is then compared with the value in "STRENGTH THRESHOLD" register. If STRENGTH exceeds the STRENGTH THRESHOLD, this is considered a final, filtered TOUCH status. In data filtering stage, 3 modes of operation is supported: Mode 1: Only the "touch" channel with highest STRENGTH is taken Mode 2: All the "touch" channels with STRENGTH > STRENGTH THRESHOLD is taken Mode 3: The 2 "touch" channel with the highest STRENGTH is taken These modes are selected using the FEATURE SELECTOR register. The final, filtered data is accessible through the Touch Byte register.
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STMPE821
Capacitive compensation
2.2
Power management
The STMPE821 operates in 3 states. Figure 5. STMPE821 operating states
RESET ACTIVE (6.5 MHz) Host command Touch, hotkey, host command Host command HIBERNATE SLEEP (200 KHz)
Time out, host command Hotkey
CS00039
On RESET, the STMPE821 enters the ACTIVE state immediately. Upon a fixed period of inactivity, the device enters into the SLEEP state. Any touch activity in SLEEP state would cause the device to go back to ACTIVE state. In SLEEP mode: -Calibration continues if F2A bit is set in CONTROL register -Calibration stops if F2A bit is NOT set in CONTROL register (IDLE mode) If no touch activity is expected, the host may set the device into HIBERNATE state to save power.
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Power schemes
STMPE821
3
Power schemes
The STMPE821 can be powered by a 1.8 V supply directly, or 3.0 - 3.6 V supply through the internal voltage regulator. VIO powers all the GPIOs directly, if LED driving is required on the GPIO, VIO should be at least 3.3 V. Figure 6. Power using the internal regulator
VIO
3 - 5.5 V
STMPE821
VCC
GND
CS00048
Figure 7.
Power bypassing the internal regulator
VIO
1.65 - 5.5 V
STMPE821
VCC
1.65 - 1.95 V
GND
CS00051
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STMPE821
I2C interface
4
I2C interface
The features that are supported by the I2C interface are the following ones:

I2C slave device Compliant to Philips I2C specification version 2.1 Supports standard (up to 100 kbps) and fast (up to 400 kbps) modes. 7-bit and 10-bit device addressing modes General call Start/Restart/Stop I2C address is 0x58 (0xB0/0xB1 for write/read, including the LSB)
Start condition A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and will not respond to any transaction unless one is encountered. Stop condition A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers. Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it would to not acknowledge the receipt of the data. Data Input The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low. Memory addressing For the bus master to communicate to the slave device, the bus master must initiate a Start condition and followed by the slave device address. Accompanying the slave device address, there is a Read/WRITE bit (R/W). The bit is set to 1 for read and 0 for write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.
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I2C interface Table 4.
Mode
STMPE821 Operation modes
Byte Programming sequence Start, Device address, R/W = 0, Register address to be read Restart, Device address, R/W = 1, Data Read, STOP If no Stop is issued, the Data Read can be continuously performed. If the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after every byte of data being read. For those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write operations. Refer to the memory map table for the address ranges that are auto and non-increment. An example of such a non-increment address is FIFO Start, Device address, R/W = 0, Register address to be written, Data Write, Stop If no Stop is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address autoincrement, then the register address auto-increments internally after every byte of data being written in. For those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write operations. Refer to the memory map table for the address ranges that are auto and non-increment. An example of a non-increment address is Data port for initializing the PWM commands.
Read
1
Write
1
Figure 8.
One byte Read
Read and write modes (random and sequential)
Ack Restart R/W=0 R/W=1 Device Address Reg Address Device Address Data Read No Ack
Start
Stop
Ack
Ack
Ack Restart
More than one byte Read
Device Address
Reg Address
Device Address
Data Read
Data Read + 1
No Ack
R/W=0
R/W=1
Data Read + 2
Start
Ack
One byte Write
Device Address
Reg Address
Data to be written
R/W=0
Start
R/W=0
Data to Write + 1
Start
Data to Write + 2
Master Slave
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Ack Stop
Ack
Ack
Ack
Ack
More than one byte Read
Device Address
Reg Address
Data to Write
Ack Stop
Ack
Ack
Ack
Ack
Stop
Ack
STMPE821
Register map and function description
5
Register map and function description
This section lists and describes the registers of the STMPE821 device, starting with a register map and then provides detailed descriptions of register types. Table 5.
Address 0x00 0x01 0x02 0x03 0x04 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x10 0x12 0x14 0x16 0x18 0x20 0x21 0x22 0x23 0x25 0x26 0x27 0x28 0x29 0x2A 0x30 0x37
Register summary map table
Register name CHIP_ID_0 CHIP_ID_1 ID_VER SYS_CFG_1 SYS_CFG_2 INT_CTRL INT_EN INT_STA GPIO__INT_EN_lsb GPIO__INT_EN_msb GPIO_INT_STA_lsb GPIO_INT_STA_msb GPIO_MR GPIO_SET GPIO_DIR GPIO_FUNCT TOUCH_FIFO FEATURE_SEL ETC_WAIT CAL_INTERVAL INTEGRATION_ TIME CTRL INT_MASK INT_CLR FILTER_PERIOD FILTER_THRESHOL D REF_DLY TVR Bit 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 64 8 8 8 8 8 8 8 8 8 8 8 Type R R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset value 0x08 0x21 0x01 0x00 0xEF 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x27 0x30 0x0F 0x00 0x08 0x00 0x00 0x00 0x00 0x08 Function Device identification Device identification Revision number System configuration 1 System configuration 2 Interrupt control register Interrupt enable register Interrupt status register GPIO interrupt enable register GPIO interrupt enable register GPIO interrupt status register GPIO interrupt status register GPIO monitor pin GPIO set pin state register GPIO set pin direction register GPIO function register Fifo access for touch data buffer Feature selection Wait time Calibration interval Integration time Control Interrupt mask Interrupt clear Filter period Filter threshold Reference delay Touch variance setting
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Register map and function description Table 5.
Address 0x40 0x50 0x57 0x60 0x67 0x70 0x77 0x80 0x87 0x90 0x91 0x92 0xA0 0xA1 0xB0 0xB1 0xB2 0xB4 0xB5 0xB6 0xB8 0xB9 0xBA 0xBC 0xBD 0xBE
STMPE821
Register summary map table (continued)
Register name EVR STRENGTH_THRES [0-7] STRENGTH [0-7] CAL_IMPEDANCE [0-7] IMPEDANCE [0-7] TOUCH_BYTE_L TOUCH_BYTE_H INT_PENDING PWM_OFF_OUTPUT MASTER_EN PWM0_SET PWM0_CTRL PWM0_RAMP_RATE PWM1_SET PWM1_CTRL PWM1_RAMP_RATE PWM2_SET PWM2_CTRL PWM2_RAMP_RATE PWM3_SET PWM3_CTRL PWM3_RAMP_RATE Bit 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Type R/W R/W R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset value 0x04 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Function Enviromental variance Setting of strength threshold for each channel Strenght Calibrated impedance Impedance Touch sensing data output Touch sensing data output Status of GINT interrupt sources PWM group control Master enable PWM 0 setup PWM 0 control PWM 0 ramp rate PWM 1 setup PWM 1 control PWM 1 ramp rate PWM 2 setup PWM 2 control PWM 2 ramp rate PWM 3 setup PWM 3 control PWM 3 ramp rate
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STMPE821
System and identification registers
6
System and identification registers
Table 6.
Address 0x00 0x01 0x02 0x03 0x04
System and identification registers map
Register name CHIP_ID_0 CHIP_ID_1 ID_VER SYS_CFG_1 SYS_CFG_2 Bit 16 16 8 8 8 Type R R R R/W R/W Reset 0x08 0x21 0x01 0x00 0xEF Function Device identification Device identification Revision number System configuration 1 System configuration 2
CHIP_ID_x
Address: Type: Reset: Description:
0x00, 0x01 R 0x08, 0x21
Device identification
16-bit device identification
ID_VER
Address: Type: Reset: Description:
0x02 R
Revision number
0x01 16-bit revision number
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System and identification registers
STMPE821
SYS_CFG_1
7 6 RESERVED 5
System configuration 1
4 3 SLEEP 2 WARM_RESET 1 SOFT_RESET 0 HIBERNATE
Address: Type: Reset: Description:
0x03 R/W
0x00 The reset control register enables to reset the device
[7:4] RESERVED [3] SLEEP: Write `1' to enable sleep mode [2] WARM_RESET: Write `1' to initiate a warm reset. Register content remains, state machine reset. [1] SOFT_RESET: Write `1' to initiate a soft reset. All registers content and state machines reset. [0] HIBERNATE: Force the device into hibernation mode. Write `1' to enter the hibernate mode,
SYS_CFG_2
7 SENSOR CLOCK 2 6 SENSOR CLOCK 1 5 SENSOR CLOCK 0
System configuration 2
4 3 PWM CLOCK DISABLE 2 GPIO CLOCK DISABLE 1 FIFO CLOCK DISABLE 0 TOUCH CLOCK DISABLE
-
Address: Type: Reset: Description:
0x04 R/W
0xEF This register enables to switch off the clock supply
[7:5] SENSOR CLOCK: See description in the table below. [4] RESERVED [3] PWM CLOCK DISABLE: Write `1' to disable the clock to PWM unit. [2] GPIO CLOCK DISABLE: Write `1' to disable the clock to GPIO unit. Note that GPIO clock is required for PWM operation. [1] FIFO CLOCK DISABLE: Write `1' to disable the clock to FIFO unit. This must be set to `0' if touch interrupt is required. [0] TOUCH CLOCK DISABLE: Write `1' to disable the clock to TOUCH unit.
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STMPE821 Table 7.
Mode
System and identification registers Sensor clock setting
Divider 1 2 Operational (6.5 MHz) 4 8 16 1 2 Autosleep (200 KHz) 4 8 16 Sensor clock [2:0] 000 001 010 011 1xx 000 001 010 011 1xx Active 12.8 KHz 6.4 KHz 3.2 KHz 1.6 KHz 800 Kz 400 Hz 200 Hz 100 Hz 50 Hz 25 Hz Calibration 100 KHz 50 KHz 25 KHz 12.5 KHz 6.25 KHz 3.2 KHz 1.6 KHz 800 Hz 400 Hz 200 Hz Idle 400 Hz 200 Hz 100 Hz 50 Hz 25 Hz 12.5 Hz 6.2 Hz 3.1 Hz 1.5 Hz 0.75 Hz
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Interrupt controller module
STMPE821
7
Interrupt controller module
Figure 9. Interrupt controller module block diagram
Interrupt INT pending status INT AND
Interrupt INT mask enable
GPIO interrupt status AND
GPIO interrupt enable
CS00053
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STMPE821
Interrupt controller module
INT_CTRL
7 6 5
Interrupt control register
4 3 2 POLARITY 1 TYPE 0 INT_EN
Address: Type: Reset: Description:
0x08 R/W 0x00 This register is used to enable control the polarity, edge/level and enabling of the interrupt system.device
[7:3] RESERVED [2] POLARITY: '0' for active low '1' for active high [1] TYPE: '0' for level trigger '1' for edge trigger (pulse width is 200 uS) [0] INT_EN: '0' to disable all interrupt '1' to enable all interrupt
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Interrupt controller module
STMPE821
INT_EN
7 GPIO 6 PWM3 5 PWM2
Interrupt enable register
4 PWM1 3 PWM0 2 GEN 1 FIFO 0 POR
Address: Type: Reset: Description:
0x09 R/W
0x00 This register is used to enable the interruption from a system related interrupt source to the host. Writing `1' in this register enables the corresponding interrupt event to generate interrupt signal at the INT pin. Note that even if the interrupt is not enabled, an interrupt event will still be reflected in the interrupt status register.
[7] GPIO: One or more level transition in enabled GPIOs [6] PWM3: Completion of PWM sequence [5] PWM2: Completion of PWM sequence [4] PWM1: Completion of PWM sequence [3] PWM0: Completion of PWM sequence [2] GEN: System INT (A21, I2A, EOC) [1] FIFO: Data available in FIFO [0] POR: Power-on reset
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STMPE821
Interrupt controller module
INT_STA
7 GPIO 6 PWM3 5 PWM2
Interrupt status register
4 PWM1 3 PWM0 2 GEN 1 FIFO 0 POR
Address: Type: Reset: Description:
0x0A R
0x00 This register is used to enable the interruption from a system related interrupt source to the host. Regardless whether the IESYSIOR bits are enabled, the ISSYSIOR bits are still updated. Writing `1' clears a bit in this register. Writing `0' has no effect.
[7] GPIO: One or more level transition in enabled GPIOs [6] PWM3: Completion of PWM sequence [5] PWM2: Completion of PWM sequence [4] PWM1: Completion of PWM sequence [3] PWM0: Completion of PWM sequence [2] GEN: System INT (A21, I2A, EOC) [1] FIFO: Data available in FIFO [0] POR: Power-on reset
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Interrupt controller module
STMPE821
GPIO_INT_EN
7 6 5
GPIO interrupt enable registerI
4 3 IEG[x] 2 1 0
Address: Type: Reset: Description:
0x0B, 0x0C R/W 0x00 The GPIO interrupt enable register is used to enable the interruption from a particular GPIO interrupt source to the host. The IEg[7:0] bits and the interrupt enable mask bits correspond to the GPIO[7:0} pins.
[7:0] IEG[7:0] Interrupt enable GPIO mask (where x = 7 to 0) Writing a `1' to the IE[x] bit will enable the interruption to the host.
GPIO_INT_STA
7 6 5
GPIO interrupt status register
4 3 2 1 0
Address: Type: Reset: Description:
0x0D R/W
0x00 The GPIO interrupt status register LSB monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless whether the IEGPIOR bits are enabled or not, the INT_STA_GPIO_LSB bits are still updated. The ISG[7:0] bits are the interrupt status bits correspond to the GPIO[7:0] pins.
[7:0] ISG[x]: Interrupt status GPIO (where x = 7 to 0) Read: Interrupt status of the GPIO[x]. Writing `1' clears a bit. Writing `0' has no effect.
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STMPE821
GPIO controller
8
GPIO controller
A total of 8 GPIOs are available in the STMPE821. The GPIO controller contains the registers that allow the host system to configure each of the pins into either a GPIO, direct output of a TOUCH channel or a PWM output. Unused GPIOs should be configured as outputs to minimize the power consumption. A group of registers is used to control the exact function of each of the 8 GPIOs. The registers and their respective address is listed in the following table. Table 8. GPIO controller registers summary map
Register name GPIO_MR_LSB GPIO_MR_MSB GPIO_SET_LSB GPIO_SET_MSB GPIO_DIR_LSB GPIO_DIR_MSB GPIO_FUNCT_LSB GPIO function register 0x17 GPIO_FUNCT_MSB YES Description GPIO monitor pin state register GPIO set pin state register GPIO set pin direction register Auto-increment YES
Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16
YES
YES
All GPIO registers are named as GPxx, where: Xxx represents the functional group For LSB registers:
7 IO-7
6 IO-6
5 IO-5
4 IO-4
3 IO-3
2 IO-2
1 IO-1
0 IO-0
For MSB registers:
7
6
5
4
3 RESERVED
2
1
0
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GPIO controller The function of each bit is shown in the following table: Table 9. GPIO control bits function
Function
STMPE821
Register name GPIO monitor pin state GPIO set pin state
Reading this bit yields the current state of the bit. Writing has no effect. Writing '1' to this bit causes the corresponding GPIO to go to '1' state Writing '0' to this bit causes the corresponding GPIO to go to '0' state '0' sets the corresponding GPIO to input state, and '1' sets it to output state. All bits are '0' on reset. The GPIO must be set as output if the PWM on this pin is to be used. '1' sets the corresponding GPIO to function as GPIO/PWM, and '0' sets it to touchkey direct output mode. For GPIO 0-3, if the GPIO function is set to GPIO/PWM mode and the AF bits in the PWM master enable register is enabled, the corresponding GPIO will function as PWM output.
GPIO set pin direction
GPIO function
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STMPE821
Capacitive touch module registers
9
Capacitive touch module registers
Table 10. TOUCH_FIFO summary table
Address 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Function
FIFO-0, LSB FIFO-0, MSB FIFO-1, LSB FIFO-1, MSB FIFO-2, LSB FIFO-2, MSB FIFO-3, LSB FIFO-3, MSB
TOUCH_FIFO
7 6 5
Touch FIFO
4 3 2 1 0
T7
T6
T5
T4
T3
T2
T1
T0
Address: Type: Reset: Description:
0x19, 0x18 R 0x00 TOUCH_FIFO is the access port for the internal 4-level FIFO used for buffering the touch events. While it is possible to access each bytes in the data structure directly, it is recommended that the FIFO is accessed only via the 0x18 address. The FIFO must be accessed in multiples of 2 bytes (LSB, MSB). For STMPE821, MSB is reserved and LSB contains a snapshot of the recent touch event. The FIFO must be accessed in multiples of 2 bytes (LSB, MSB). For STMPE821, MSB is reserved and LSB contains a snapshot of the recent touch event. Where Tn is touch status of touch sensing channel n.
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Capacitive touch module registers
STMPE821
FEATURE_SELECT
7 6 RESERVED 5
Feature select
4 3 AFS3 2 AFS2 1 AFS1 0 Filter EN
Address: Type: Reset: Description:
0x20 R/W
0x04 Controls AFS (advanced filtering system and second level filtering feature
[7:4] RESERVED [3] AFS3: Write '1' to enable AFS mode 3 [2] AFS2: Write '1' to enable AFS mode 2 [1] AFS1: Write '1' to enable AFS mode 1 [0] Filter EN: Write '1' to enable filter
ETC_WAIT
7 6 5
Wait time setting
4 3 ETC_WAIT[7:0] 2 1 0
Address: Type: Reset: Description:
0x21 R/W
0x27 Sets the wait time between the calibration and the last button touch
[7:0] ETC_WAIT[7:0]: ETC wait time = ETC_Wait[7:0] *64 + sensor clock period A "non-touch" condition must persist for this wait time, before an ETC operation is carried out. Range: 800 mS - 12.8 S
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STMPE821
Capacitive touch module registers
CAL_INTERVAL
7 6 5
Calibration interval
4 3 CAL_INTERVAL 2 1 0
Address: Type: Reset: Description:
0x22
R/W
0x30 Calibration interval
[7:0] CALIBRATION INTERVAL: Interval between calibration = Calibration Interval [7:0] * sensor clock period * 50 Range: 625 mS - 10 S
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Capacitive touch module registers
STMPE821
INTEGRATION TIME
7 6 5
Integration time
4 3 INTEGRATION_TIME[7:0] 2 1 0
Address: Type: Reset: Description:
0x23
R/W
0x0F Integration time
[7:0] Integration time in AFS mode Total period of integration = sensor clock period * Integration Time [7:0] 50uS - 800uS
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STMPE821
Capacitive touch module registers
CTRL
7 6 RESERVED 5
Control
4 3 F2A 2 HDC_U 1 HDC_C 0 HOLD
Address: Type: Reset: Description:
0x25 R/W
0x00 Control
[7:4] 0x90 [3] F2A: Write '1' to force device to remain in ACTIVE state at all times [2] HDC_U: Write '1' to perform unconditional host driven calibration. Cleared to '0' when calibration is completed Only applicable HOLD is '1' [1] HDC_C: Write '1' to perform conditional host driven calibration. Calibration is performed if and only if no touch is detected. Cleared to '0' when calibration is completed Only applicable HOLD is '1' [0] HOLD: '0' to enable ETC '1' to disable ETC
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Capacitive touch module registers
STMPE821
INT_MASK
7 6 RESERVED 5
Interrupt mask
4 3 EOC 2 I2A 1 A2I 0 RESERVED
Address: Type: Reset: Description:
0x26 R/W
0x08 Writing '1' to this register disables the corresponding interrupt source.
[7:4] RESERVED [3] EOC: End of calibration This interrupt occurs on both automatic and forced calibration [2] I2A: SLEEP to Active transition [1] A2I: Active to SLEEP transition [0] RESERVED
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STMPE821
Capacitive touch module registers
INT_CLR
7 6 RESERVED 5
Interrupt clear
4 3 EOC 2 I2A 1 A2I 0 RESERVED
Address: Type: Reset: Description:
0x27 R/W
0x00 Writing '1' to this register clears the corresponding interrupt source in INT_PENDING register.
[7:4] 0x90 [3] EOC: End of calibration This interrupt occurs on both automatic and forced calibration [2] I2A: SLEEP to Active transition [1] A2I: Active to SLEEP transition [0] RESERVED
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Capacitive touch module registers
STMPE821
FILTER_PERIOD
7 6 5
Filter period
4 3 FILTER_COUNT 2 1 0
Address: Type: Reset: Description:
0x28 R/W
0x00 Filter period.
[7:0] FILTER_COUNT: Additional filter to stabilize touch output in AFS mode. AFS touch output is monitored for Filter Count [7:0] times every integration time. For each time a "touch status" is detected, an internal "Filter Counter" is incremented once. This counter value is then compared with Filter Threshold (register 0x3E)
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STMPE821
Capacitive touch module registers
FILTER_THRESHOLD
7 6 5
Filter threshold
4 3 FILTER_THRESHOLD 2 1 0
Address: Type: Reset: Description:
0x29 R/W
0x00 Filter threshold.
[7:0] FILTER_THRESHOLD: An internal "Filter Counter" is compared with Filter Threshold [7:0] to determine if a valid touch has occurred.
REFERENCE_DELAY
7 RESERVED 6 5
Reference delay
4 3 2 1 0 REFERENCE_DELAY
Address: Type: Reset: Description:
0x2A R/W
0x00 Shifting of capacitive sensor dynamic range. The capacitance value set into this register is in effect, equivalent to capacitor connected to the S_Ref pin.
[7] RESERVED [6:0] REFERENCE_DELAY: Valid range = 0-127 Each step represents capacitance value of 0.06 pF Warm reset is required after this value is updated
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Capacitive touch module registers
STMPE821
TVR
7 RESERVED 6 5
Touch variance setting
4 3 TVR 2 1 0
Address: Type: Reset: Description:
0X30 - 0x3B R/W
0x08 Touch variance setting.
[7] RESERVED [6:0] TVR: Setting TVR between 0-99 A high TVR value decreases sensitivity of the sensor, but increasing its tolerance to ambient noise A small TVR value increases the sensitivity.
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STMPE821
Capacitive touch module registers
EVR
7 RESERVED 6 5
Enviromental variance
4 3 TVR 2 1 0
Address: Type: Reset: Description:
0x40 R/W
0x04 Enviromental variance setting.
[7] RESERVED [6] EVR: EVR is used to detect "Non-Touch" condition
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Capacitive touch module registers
STMPE821
STRENGTH_THRESHOLD
7 6 5
Strength threshold
4 3 STRENGTH_THRESHOLD 2 1 0
Address: Type: Reset: Description:
0x50 - 0x5B R/W
0x01 Strength threshold.
[7:0] STRENGTH_THRESHOLD: Setting threshold to be used in AFS mode to determine valid touch
STRENGTH
7 6 5
Strength
4 STRENGTH 3 2 1 0
Address: Type: Reset: Description:
0x60 - 0x67 R 0x00 The number of times where a sense capacitance exceeds the calibrated reference impedance
[7:0] STRENGTH: Read-only field Counts the number of times a sensed impedance exceeds calibrated reference impedance over and integration time. Maximum strength equals Integration Time [7:0]
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STMPE821
Capacitive touch module registers
CALIBRATED_IMPEDANCE
7 6 5
Calibrated impedance
4 3 2 1 0 CAL_IMPEDANCE
Address: Type: Reset: Description:
0x70 - 0x77 R 0x00 Calibrated impedance is an integral reference value maintained by the device.
[7:0] CALIBRATED IMPEDANCE: Calibrated reference impedance
IMPEDANCE
7 6 5
Impedance
4 IMPEDANCE 3 2 1 0
Address: Type: Reset: Description:
0x80 - 0x87 R 0x00 Impedance is the instantaneous impedance value seen at the input pin of eac cap. sensing pin.
[7:0] IMPEDANCE: Currently sensed impedance
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Capacitive touch module registers
STMPE821
TOUCH_BYTE_L
7 6 5
Touch byte L
4 TOUCH 3 2 1 0
Address: Type: Reset: Description:
0x90 R 0x00 Touch status of capacitive channel 0 - 7.
[7:0] TOUCH: Reads '1' if the corresponding capacitance sensing channel reads a valid TOUCH
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STMPE821
Capacitive touch module registers
TOUCH_BYTE_H
7 6 5
Touch byte H
4 RESERVED 3 2 1 0
Address: Type: Reset: Description:
0x91 R 0x00 Reserved.
[7:0] RESERVED:
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Capacitive touch module registers
STMPE821
INT_PENDING
7 6 RESERVED 5
Interrupt pending
4 3 EOC 2 I2A 1 A21 0 RESERVED
Address: Type: Reset: Description:
0x92 R/W 0x00 Reflects the status of each interrupt source.
[7:4] RESERVED [3] EOC: End of calibration [2] I2A: SLEEP to active transition [1] A21: Active to SLEEP transition [0] RESERVED
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STMPE821
Basic PWM controller
10
Basic PWM controller
The advanced PWM allows complex brightness and blinking control of a LED. The basic PWM controller allows simpler brightness control and basic blinking patterns. The STMPE821 is fitted with a 4-channel basic PWM controller. The PWM controllers outputs are connected to the GPIO 0-3. In order to activate the PWM channels, the alternate function bits in the master enable register must be set to '1'. The PWM controllers are capable of generating the following brightness patterns: Figure 10. Pulses with programmable brightness, ON/OFF period and repetition
1 time Duty cycle unit
Time On period Off period ON period Off period
CS00054
On period = period 0[1:0] * time unit [3:0] Off period = period 1[1:0] * time unit [3:0] Duty cycle during "on period" = brightness [7:4] Number of cycles = repetition [3:0] Ramp mode is disabled Figure 11. Ramps with programmable brightness, ON/OFF period and repetition
Duty cycle
1 time unit
Time ON period Off period ON period Off period
CS00055
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Basic PWM controller "On" period = period 0[1:0] * time unit [3:0] "Off" period = period 1[1:0] * time unit [3:0] Duty cycle during "on" period = brightness [7:4] Number of cycles = repetition [3:0] Ramp up rate is programmable. Figure 12. Fixed brightness output
STMPE821
Duty cycle
time unit
Time
CS00056
"On" period = period 0[1:0] * time unit [3:0] Off period = don't care Duty cycle during "on" period = brightness [7:4] Number of cycles = repetition [3:0] = 0 (means infinite repetition)
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STMPE821
Basic PWM controller
10.1
PWM function register map
Table 11. PWM function register map summary table
Description Set the output level when PWM is disabled Enables/disables individual basic PWM channels PWM 0 setup PWM 0 control PWM 0 ramp rate PWM 1 setup PWM 1 control PWM 1 ramp rate PWM 2 setup PWM 2 control PWM 2 ramp rate PWM 3 setup PWM 3 control PWM 3 ramp rate Auto-increment (during sequential R/W) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Register name
PWM_OFF_OUTPUT MASTER_EN PWM0_SET PWM0_CTRL PWM0_RAMP_RATE PWM1_SET PWM1_CTRL RAMP1_RATE PWM2_SET PWM2_CTRL RAMP2_RATE PWM3_SET PWM3_CTRL PWM3_RATE
MASTER_EN
7 AF3 6 AF2 5 AF2
Master enabler
4 AF0 3 EN3 2 EN2 1 EN1 0 EN0
Address: Type: Reset: Description:
0xA1 R/W 0x00 Write `1' to select PWM function on the corresponding channel.
[7:4] AF3:0 [3:0] OUT3:0: Default is '0'. Write `1' to used the corresponding PWM channel must be diabled for the controlling registers to be accessed.
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Basic PWM controller
STMPE821
PWM_OFF_OUTPUT
7 6 5
PWM group control register
4 3 OUT3 2 OUT2 1 OUT1 0 OUT0
Address: Type: Reset: Description:
0xA0 R/W 0x00 PWM group control register.
[7:4] RESERVED [3:0] OUT3:0: Default is '0' '1' - PWM channel outputs '1' when disabled '0' - PWM channel outputs '0' when disabled
RAMP_RATE
7 RESERVED 6 5
Ramp rate register
4 RAMP_DOWN 3 2 1 RAMP_UP 0
Address: Type: Reset: Description:
0xB2 R/W 0x00 Ramp rate register.
[7:6] RESERVED [5:3] RAMP_DOWN [2:0]: '000' = 1/4 of time unit per brightness level change '001' = 1/8 of time unit per brightness level change '010' = 1/16 of time unit per brightness level change '011' = 1/32 of time unit per brightness level change '100' = 1/64 of time unit per brightness level change '101' = 1/128 of time unit per brightness level change '110' = reserved '111' = reserved [2:0] RAMP_UP [2:0]: '000' = 1/4 of time unit per brightness level change '001' = 1/8 of time unit per brightness level change '010' = 1/16 of time unit per brightness level change '011' = 1/32 of time unit per brightness level change '100' = 1/64 of time unit per brightness level change '101' = 1/128 of time unit per brightness level change '110' = reserved '111' = reserved
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STMPE821
Basic PWM controller
PWM_n_SETUP
7 6 BRIGHTNESS 5
PWM_n setup register (n=0-3)
4 3 2 TIMING 1 0
Address: Type: Reset: Description:
0xB0 R/W 0x00 PWM setup register.
[7:4] BRIGHTNESS: This defines the duty cycle during the ON period of the PWM channel output which in turn determines the brightness level of the LED that the PWM output drives. 0000: Duty cycle ratio 1:15 ( 6.25%, minimum brightness) 0001: Duty cycle ratio 2:14 ( 12.50%) 0010: Duty cycle ratio 3:13 ( 18.75%) 0011: Duty cycle ratio 4:12 ( 25.00%) 0100: Duty cycle ratio 5:11 ( 31.25%) 0101: Duty cycle ratio 6:10 ( 37.50%) 0110: Duty cycle ratio 7: 9 ( 43.75%) 0111: Duty cycle ratio 8: 8 ( 50.00%) 1000: Duty cycle ratio 9: 7 ( 56.25%) 1001: Duty cycle ratio 10: 6 ( 62.50%) 1010: Duty cycle ratio 11: 5 ( 68.75%) 1011: Duty cycle ratio 12: 4 ( 75.00%) 1100: Duty cycle ratio 13: 3 ( 81.25%) 1101: Duty cycle ratio 14: 2 ( 87.50%) 1110: Duty cycle ratio 15: 1 ( 93.75%) 1111: Duty cycle ratio 16: 0 (100.00%, maximum brightness) [3:1] TIMING[3:0] is the time unit from which the duration of the ON period and OFF period is defined in: "000" = 20 mS "001" = 40 mS "010" = 80 mS "011" = 160 mS "100" = 320 mS "101" = 640 mS "110" = 1280 mS "111" = 2560 mS [0] Write '1' to activate ramp mode
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Basic PWM controller
STMPE821
PWM_CTRL_n
7 PERIOD_0 6 5
PWM control register n=0-3
4 PERIOD_1 3 2 REPETITION 1 0 FRAME_ORDER
Address: Type: Reset: Description:
0xB1, 0xB5, 0xB9, 0xBD R/W 0x00 This register controls the sequence and repetition of blinking.
[7:6] PERIOD_0: This defines the ON period time which is when the PWM channel output is toggling. The time unit is as defined in the TIMING bits of the respective TIMING_SETUP registers: 00: 1 time unit 01: 2 time unit 10: 3 time unit 11: 4 time unit [5:4] PERIOD_1: This defines the OFF period time which is when the PWM channel output is low, that is, not toggling. The time unit is as defined in the TIMING bits of the respective TIMING_SETUP registers: 00: 0 time unit. This means that there is no OFF period but only ON period, that is, the PWM channel output will always be toggling. 01: 1 time unit 10: 2 time unit 11: 3 time unit [3:1] REPETITION: This defines the number of repetition of pairs of PERIOD_0 and PERIOD_1. 000: infinite repetition. 001: execute only one pair. 010: execute 2 pairs 011: execute 3 pairs 100: execute 4 pairs 101: execute 5 pairs 110: execute 6 pairs 111: execute 7 pairs [0] FRAME_ORDER: For PWM mode, this defines which frame, PERIOD_0 or PERIOD_1 comes first. 0: PERIOD_0 is outputted first then PERIOD_1. 1: PERIOD_1 is outputted first then PERIOD_0.
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STMPE821
Basic PWM controller
10.2
Interrupt on basic PWM controller
The basic PWM controller can be programmed to generate interrupts on completion of the blinking sequence. a) b) Each basic PWM controller has its own bit in interrupt the enable/status registers. If enabled, completion in any of the PWM controller triggers interrupts. No interrupt is generated if infinite repetition is set.
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Maximum rating
STMPE821
11
Maximum rating
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 12.
Symbol VCC VIO VESD Power supply GPIO supply voltage ESD protection on each GPIO/touch pin
Absolute maximum ratings
Value Parameter Min Typ Max 2.5 6.0 8 V V kV Unit
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STMPE821
Electrical specifications
12
Electrical specifications
Table 13.
Symbol VCC VIO Iactive Iactive Iactive Isleep Ihibernate VIL VIH VIL VIH VOL VOH VOL VOH
DC electrical characteristics (-40 -85 C unless otherwise stated))
Value Parameter Core supply voltage IO supply voltage Active current Active current Active current Sleep current Hibernate current Input voltage low state (reset/I2C) Input voltage high state (reset/I2C) Input voltage low state (GPIO) Input voltage high state (GPIO) Output voltage low state (GPIO) VCC = 1.8 V VCC = 1.8 V VIO = 1.8 -5.0 V VIO = 1.8 -5.0 V VIO = 1.8 V, IOL = 4 mA -0.3 V 0.65 VCC -0.3 VIO 0.65 VIO -0.3 V 0.75 VIO -0.3 V 0.75 VIO 5% touch activity 10% touch activity 100% touch activity Test condition Min 1.65 1.65 Typ Max 1.95 5.5 63 90 550 40 7 0.35 VCC VCC+0.3 V 0.35 VIO VIO+0.3 V 0.25 VIO VIO+0.3 V 0.25 VIO VIO+0.3 V V V A A A A A V V V V V V V V Unit
- -
42 60 350 25 4
Output voltage high state VIO = 1.8 V, IOL = 4 mA (GPIO) Output voltage low state (GPIO) VIO = 3.3 -5.0 V, IOL = 8 mA
Output voltage high state VIO = 3.3 -5.0 V, IOL = 8 mA (GPIO) VIN = 5.5 V, VIO = 5.5 V All GPIOs
ILEAKAGE Input leakage current
0.05
0.5
A
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Package mechanical data
STMPE821
13
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 13. QFN16L (2.6 x 1.8 mm) package outline
BOTTOM VIEW
QFN16L
1. Drawing not to scale. 2. Dimensions are in millimeters.
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STMPE821 Table 14. QFN16L (2.6 x 1.8 mm) mechanical data
millimeters Symbol Typ A A1 b D E e L 0.55 0.02 0.20 2.60 1.80 0.40 0.40 0.35 Min 0.45 0 0.15 2.50 1.70
Package mechanical data
Max 0.60 0.05 0.25 2.70 1.90
0.45
Figure 14. QFN16L (2.6 x 1.8 mm) footprint recommentations
7874009
1. Drawing not to scale. 2. Dimensions are in millimeters.
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Package mechanical data
STMPE821
Figure 15. QFN16L (2.6 x 1.8 mm) carrier tape
785978-J
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STMPE821 Figure 16. QFN16L (2.6 x 1.8 mm) reel information
Package mechanical data
7875978
1. Drawing not to scale. 2. Dimensions are in millimeters
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Revision history
STMPE821
14
Revision history
Table 15.
Date 26-Feb-2008
Document revision history
Revision 1 Initial release. Modified: operating voltage range so as to included support for 5.5 V, Section 1.3 on page 6, Figure 5 on page 9, Section 4 on page 11, Section 5 on page 13, Section 8 on page 23, Added: PWM_CTRL_n register description and ILEAKAGE value in Table 13 on page 49 Changes
10-Jun-2008
2
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STMPE821
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